Following fabrication, semiconductor memory devices often undergo a number of functional tests to determine their suitability for commercial sale. Such testing may be performed to evaluate functions of peripheral circuits and memory cells forming the semiconductor memory devices. Many of the semiconductor memory devices tend to exhibit single bit failures rather than dual bit and/or cluster bit failures. Accordingly, as the semiconductor memory devices become more complex and achieve higher levels of integration, their test time also increases. To reduce the test time, a parallel test has been proposed. The parallel test may be performed by simultaneously writing the same data into a plurality of memory cells of the semiconductor memory device and by simultaneously reading the data stored in the plurality of memory cells.
In general, test input/output (I/O) lines in addition to global I/O lines may be required to perform the parallel test. Accordingly, when a read operation is executed in the parallel test mode, the data stored in the memory cells may be loaded onto a plurality of test I/O lines whose data levels are detected or sensed to determine the functionality of the memory cells. In other words, during the parallel test mode, the data stored in the memory cells may be supplied through the test I/O lines instead of the global I/O lines through which the data stored in the memory cells are supplied during a normal read mode.
A semiconductor memory device may be designed to have one of various bit organizations such as “×4”, “×8”, “×16”, “×32” and the like. For example, a semiconductor memory device that has a bit organization of “×16” is adapted to store 16 bits of data during a write operation or supply 16 bits of data during a read operation.